1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same. More specifically, the present invention relates to a semiconductor device with a super junction structure and a manufacturing method of the same.
2. Description of the Related Art
In recent years, there are increasing demands for thin-shaped, lightweight electronic apparatuses represented by a liquid crystal TV, a plasma TV, and an organic EL TV. In connection with such demands, there are other strong demands for small-sized high-performance power supply devices. In response to such demands, for example, efforts have been made to improve the performance of a power semiconductor, such as improvements in properties of withstand voltage (breakdown voltage), high current, low loss, high speed, and high breakdown voltage. For example, a power MOSFET has been known as a switching element for power electronics.
The on-resistance and the breakdown voltage of MOSFET depend on the impurity concentration of its conductive layer, an N region, to a great extent. The impurity concentration of the conduction layer is made high to reduce the on-resistance. For securing a desired breakdown voltage, however, it is difficult to increase the impurity concentration higher than a certain level. In other words, in the MOSFET, a semiconductor region that connects a source region and a drain region is generally called a drift region (drift layer). The drift region becomes a current path when the MOSFET is on. In contrast, when the MOSFET is off, the breakdown voltage of the MOSFET is retained by a depletion layer extending from a p-n junction formed between the drift region and a base region.
The on-resistance of the MOSFET depends on the electrical resistance of the conductive layer (drift region). For lowering the on-resistance of the MOSFET, the impurity concentration of the drift region may be increased to lower the electric resistance of the drift region. However, if the impurity concentration of the drift region is too high, the extent of the depletion layer becomes insufficient, causing a decrease in breakdown voltage of the MOSFET. In other words, even though lower resistance can be attained by a higher impurity concentration of the drift region, an increase in impurity concentration is limited to secure the desired breakdown voltage. In the MOSFET, therefore, there is the trade-off relationship between an increase in on-resistance and a decrease in breakdown voltage. An improvement in such a trade-off relationship has been desired for a low power consumption element.
As a technique for breaking through the trade-off, a multi-RESURF structure or a super junction structure has been known in the art (see, for example, Japanese Published Patent Application No. 2002-280555, Japanese Published Patent Application No. 2006-005275, Japanese Published Patent Application No. 2007-096344, Japanese Published Patent Application No. 2007-173418, and Japanese Published Patent Application No. 2007-116190). Hereinafter, such a technology will be collectively called a super junction.
As shown in these patent documents, the MOSFET having a drift region with a super junction structure includes: a column-shaped p-type semiconductor region (a p region, a p-type pillar region, a p-type vertical RESURF layer) and a column-shaped n-type semiconductor region (an N region, an n-type pillar region, an n-type vertical RESURF layer) are alternately arranged or periodically arranged like islands in parallel with the surface of the semiconductor substrate. In other words, the MOSFET has a vertical RESURF structure in which the p-type pillar regions and the n-type pillar regions are alternately arranged in the lateral direction in the semiconductor layer sandwiched between a source electrode and a drain electrode.
The “breakdown voltage” is held by a depletion layer extended from a p-n conjunction formed by these semiconductor regions. These semiconductors can be completely depleted by narrowing them even if the depletion area extends a little by increasing the impurity concentration for lower on-resistance. The N region of the transmissive layer causes a current flow at an ON state, while the breakdown voltage can be secured by completely depleting the P region and the N region at an off state, thereby simultaneously attained both the lower ionic resistance and high breakdown voltage of the MOSFET.
Therefore, in such a super junction structure, the performance of the MOSFET depends on the width of each p-type semiconductor region and the width of each n-type semiconductor region sandwiched between the p-type semiconductor regions. If the more the width of the p-type semiconductor region and the width of the n-type semiconductor region are reduced, the more the impurity concentration of the n-type semiconductor region can be increased. As a result, the on-resistance can be further decreased while the breakdown voltage can be further increased. As is evident from the above description, the impurity concentration is important for determining the breakdown voltage and the on-resistance.
Therefore, preferably, it is important to achieve a balance between the impurity of the p-type semiconductor region and the impurity of the n-type semiconductor region (a so-called charge balance) to cause a further increase in breakdown voltage. In other words, the impurity concentration of the p-type semiconductor region and that of the n-type semiconductor region are made equal to each other to equivalently make the impurity concentration zero, resulting in high breakdown voltage. At the time of reverse bias (OFF state), complete depletion is intended while high breakdown voltage is retained. At the time of zero bias (ON state), electric current is flown through the n-type semiconductor region doped with impurities at high concentration to realize an element with low on-resistance that exceeds the limit of a material.
Furthermore, in the semiconductor device with the super junction structure, a breakdown voltage, and an avalanche voltage depend not only on the structure of a region where the semiconductor device functions actively (which is any of regions called as an element part, an element activating region, an active region, a cell region, and a device body, where these regions will be totally represented by an element region) but also on the structure formed around the element region (a terminal region, an element-surrounding region, a peripheral structure region, and a junction termination region, where these regions will be totally represented by an termination region).
Thus, there is a difference in extent of depletion layer between the element part and the terminal part. If both the element part and the terminal part are formed so that they have an equal amount of impurities, a decrease in breakdown voltage occurs and an electric field is locally concentrated on the terminal part. As a result, the element may be damaged and the entire element may hardly obtain a sufficient breakdown voltage.
Furthermore, if there is no super junction structure on the terminal part, the occurrence of avalanche breakdown leads to the generation of electrons and holes, enhancing the electric fields of the upper and lower portions of the terminal part. An increase in breakdown current tends to break the element. In other words, the avalanche voltage decreases.
In the MOSFET with a super junction structure, therefore, it has been also desired to appropriately design the structure of the element part and the terminal part. Procedures for responding such a demand can be roughly classified into an idea of taking a measure while also forming a super junction structure on the terminal part and an idea taking a measure without forming a super junction structure on the terminal part. Any of Japanese Published Patent Application No. 2006-005275, Japanese Published Patent Application No. 2007-096344, Japanese Published Patent Application No. 2007-173418, and Japanese Published Patent Application No. 2007-116190 proposes the structure of the terminal part that employs the former idea.
The semiconductor device described in Japanese Published Patent Application No. 2006-005275 includes an element part and a terminal part. The element part is provided with a super junction structure having a first conductive type first pillar region and a second conductive second pillar region. The terminal part is provided with a super junction structure adjacent to that of the element unit and the thickness thereof in the vertical direction is smaller than that of the element part. Furthermore, for securing the breakdown voltage of the terminal part, the impurity concentration of an n-type semiconductor region in the terminal region is lower than that of an n-type semiconductor region in the element part. For example, the terminal part includes a first conductive type third pillar region and a second conductive type fourth pillar region. The outermost pillar region is additionally formed on part of the third or fourth pillar region, which is the nearest to the terminal part of a super junction structure. The outermost pillar region has an impurity concentration lower than that of the first and second pillar regions. A first conductive type high resistance region is formed on the third pillar region and the fourth pillar region and is provided with a resistance value higher than that of each pillar region.
For securing the breakdown voltage of the terminal part in Japanese Published Patent Application No. 2007-096344, the impurity concentration of an n-type semiconductor region in the terminal region is smaller than that of the n-type semiconductor region of the element part. For example, an ion injection area of a second conductive partition region on the outermost part of the terminal region is set to be smaller than each region of the parallel p-n layer in the inside thereof to equalize the net impurity concentration of the second conductive type partition region on the outermost side and that of each region of the parallel p-n layer on the inner side thereof.
Likewise, in Japanese Published Patent Application No. 2007-173418, a terminal part is provided with a super junction different from that of an element part. For example, n-type regions and p-type regions are formed in parallel on the principal surface of an n+ layer in the terminal part. In addition, n-type regions and p-type regions are formed in parallel on a high resistance semiconductor layer. The impurity concentration of at least one of the n-type and p-type pillar regions is gradually changed in the direction from the first to second main electrodes so that the impurity concentration of the n-type pillar region is smaller than that of the p-type pillar region on the side of the first main electrode (source electrode) but larger on the side of the second main electrode (drain electrode).
In Japanese Published Patent Application No. 2007-116190, when a semiconductor device includes an element part where a drift current flows and a terminal part around the element part, the terminal part is provided with a second n-type drift layer and a second p-type drift layer formed in at least one of directions perpendicular to each other.
On the other hand, as a method for manufacturing a super junction structure, any of the following techniques may be employed.
(1) Ion implantation is employed to introduce n-type and p-type impurities into an epitaxial layer (epitaxial silicon) independently and the formation of such an epitaxial structure is repeated several times to form a super junction structure (hereinafter, the method will be referred to as a first manufacturing method). In other words, it is a multi-epitaxial manufacturing method that repeats the same kind of epitaxial growth several times.
(2) A trench groove is formed in a thick epitaxial layer and impurities are then doped in the groove-formed side of the layer by diffusion or the like, followed by being embedded with an insulating material or a non-conductive material (hereinafter, the method will be referred to as a second manufacturing method).
(3) A trench groove is formed in a thick epitaxial layer and silicon epitaxial containing impurities is then embedded in the groove (the method will be referred to as a third manufacturing method). In other words, it is a method of filling a trench groove once formed with epitaxial growth (trench formation epitaxial method).